Board for electronic component package, electronic component package, and method of manufacturing board for electronic component package

ABSTRACT

Aboard for an electronic component package includes a wiring part on which an electronic component is disposed, wherein the wiring part includes an insulating layer, a signal transferring wiring electrically connected to the electronic component, and an electrical testing wiring electrically disconnected from the electronic component, and the electrical testing wiring includes conductive patterns formed on both surfaces of the wiring part, and conductive vias electrically connecting the conductive patterns to each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. patent application Ser. No.15/796,411, filed on Oct. 27, 2017, which is a Divisional of U.S. patentapplication Ser. No. 15/200,838, filed on Jul. 1, 2016, now U.S. Pat.No. 9,831,142, issued on Nov. 28, 2017, which claims benefit of thepriority to Korean Patent Application No. 10-2015-0155545, filed on Nov.6, 2015 with the Korean Intellectual Property Office, the disclosure ofwhich are incorporated herein by reference in their entirety.

BACKGROUND

The present disclosure relates to a board for an electronic componentpackage, an electronic component package, and a method of manufacturinga board for an electronic component package.

TECHNICAL FIELD

An electronic component package is defined as package technology forelectrically connecting an electronic component to a printed circuitboard (PCB), such as a main board of an electronic device, or the like,and protecting the electronic component from external impacts.Meanwhile, one recent main trend in the development of technologyrelated to electronic components is the reduction in size of electroniccomponents. Therefore in a package field, in accordance with a rapidincrease in a demand for miniaturized electronic components, or thelike, the implementation of an electronic component package having acompact size and including a plurality of pins has been demanded.

One package technology suggested in order to satisfy the technicaldemands as described above is a wafer level package (WLP) using aredistribution wiring of an electrode pad of an electronic componentformed on a wafer. An example of the wafer level package includes afan-in wafer level package and a fan-out wafer level package. Inparticular, the fan-out wafer level package has a compact size and isadvantageous in implementing a plurality of pins. Therefore, recently,the fan-out wafer level package has been actively developed.

SUMMARY

An aspect of the present disclosure may provide an electronic componentpackage of which a structure is compact and manufacturing efficiency issignificantly improved by allowing an electrical test for a wiring partto be performed before an electronic component is mounted.

Another aspect of the present disclosure may provide a method ofmanufacturing an electronic component package capable of efficientlymanufacturing the electronic component package.

According to an aspect of the present disclosure, a board for anelectronic component package may include: a wiring part on which anelectronic component is disposed, wherein the wiring part includes aninsulating layer, a signal transferring wiring electrically connected tothe electronic component, and an electrical testing wiring electricallydisconnected from the electronic component, and the electrical testingwiring includes conductive patterns formed on both surfaces of thewiring part, and conductive vias electrically connecting the conductivepatterns to each other. An electrical test for the wiring part may beexecuted though an upper side of the wiring part using the electricaltesting wiring.

According to another aspect of the present disclosure, an electroniccomponent package may include: a wiring part; an electronic componentdisposed on the wiring part; and an encapsulant protecting theelectronic component. The wiring part includes an insulating layer, asignal transferring wiring electrically connected to the electroniccomponent, and an electrical testing wiring electrically disconnectedfrom the electronic component, and the electrical testing wiringincludes conductive patterns formed on both surfaces of the wiring part,and conductive vias electrically connecting the conductive patterns toeach other.

According to another aspect of the present disclosure, a method ofmanufacturing a board for an electronic component package may include:forming a wiring part on a support, the wiring part including aninsulating layer, a signal transferring wiring, and an electricaltesting wiring, and the electrical testing wiring including conductivepatterns formed on both surfaces of the wiring part, and conductive viaselectrically connecting the conductive patterns to each other;performing an electrical test for the wiring part by applying anelectrical signal to a conductive pattern formed on an upper surface ofthe wiring part; and electrically disconnecting the signal transferringwiring and the electrical testing wiring from each other such that theelectrical testing wiring is electrically disconnected from anelectronic component mounted on the wiring part and electricallyconnected to the signal transferring wiring.

According to another aspect of the present disclosure, an electroniccomponent package may include a wiring part including a plurality ofconductive patterns electrically connected to each other by viaspenetrating through a plurality of insulating layers between theplurality of conductive wirings, and an electrical testing wiringelectrically isolated from the plurality of conductive patterns, and anelectronic component disposed on the wiring part, electrically connectedto the plurality of conductive patterns of the wiring part, andelectrically isolated from electrical testing wiring.

According to another aspect of the present disclosure, a method of anelectronic component package may include forming a wiring part on asupport, the wiring part including an insulating layer, a signaltransferring wiring, and an electrical testing wiring, the electricaltesting wiring electrically connected to the signal transferring wiringthrough a connection part, performing an electrical test of the wiringpart by applying an electrical signal to a conductive pattern formed onan upper surface of the wiring part, mounting an electronic component onupper surface of the wiring part such that the electronic component iselectrically connected to the signal transferring wiring, separating thesupport from the wiring part, and removing the connection part betweenthe signal transferring wiring and the electrical testing wiring toelectrically disconnect the signal transferring wiring and theelectrical testing wiring from each other, such that the electricaltesting wiring is electrically isolated from the electronic component.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features, and advantages of the presentdisclosure will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a block diagram schematically illustrating an example of anelectronic device system;

FIG. 2 is a view schematically illustrating an example of an electroniccomponent package used in an electronic device;

FIG. 3 is a cross-sectional view schematically illustrating an exampleof an electronic component package;

FIG. 4 is a plan view schematically illustrating a shape of anelectrical testing wiring in FIG. 3;

FIGS. 5 through 12 are views schematically illustrating a board for anelectronic component package and a method of manufacturing an electroniccomponent package using the same according to an exemplary embodiment inthe present disclosure; and

FIGS. 13 through 18 are views schematically illustrating a method ofmanufacturing an electronic component package according to anotherexemplary embodiment in the present disclosure.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described asfollows with reference to the attached drawings.

The present disclosure may, however, be exemplified in many differentforms and should not be construed as being limited to the specificembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the disclosure to those skilled in the art.

Throughout the specification, it will be understood that when anelement, such as a layer, region or wafer (substrate), is referred to asbeing “on,” “connected to,” or “coupled to” another element, it can bedirectly “on,” “connected to,” or “coupled to” the other element orother elements intervening therebetween may be present. In contrast,when an element is referred to as being “directly on,” “directlyconnected to,” or “directly coupled to” another element, there may be noelements or layers intervening therebetween. Like numerals refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be apparent that though the terms first, second, third, etc. maybe used herein to describe various members, components, regions, layersand/or sections, these members, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one member, component, region, layer or section fromanother region, layer or section. Thus, a first member, component,region, layer or section discussed below could be termed a secondmember, component, region, layer or section without departing from theteachings of the exemplary embodiments.

Spatially relative terms, such as “above,” “upper,” “below,” and “lower”and the like, may be used herein for ease of description to describe oneelement's relationship to another element(s) as shown in the figures. Itwill be understood that the spatially relative terms are intended toencompass different orientations of the device in use or operation inaddition to the orientation depicted in the figures. For example, if thedevice in the figures is turned over, elements described as “above,” or“upper” other elements would then be oriented “below,” or “lower” theother elements or features. Thus, the term “above” can encompass boththe above and below orientations depending on a particular direction ofthe figures. The device may be otherwise oriented (rotated 90 degrees orat other orientations) and the spatially relative descriptors usedherein may be interpreted accordingly.

The terminology used herein describes particular embodiments only, andthe present disclosure is not limited thereby. As used herein, thesingular forms “a,” “an,” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. It willbe further understood that the terms “comprises,” and/or “comprising”when used in this specification, specify the presence of statedfeatures, integers, steps, operations, members, elements, and/or groupsthereof, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, members, elements, and/orgroups thereof.

Hereinafter, embodiments of the present disclosure will be describedwith reference to schematic views illustrating embodiments of thepresent disclosure. In the drawings, for example, due to manufacturingtechniques and/or tolerances, modifications of the shape shown may beestimated. Thus, embodiments of the present disclosure should not beconstrued as being limited to the particular shapes of regions shownherein, for example, to include a change in shape results inmanufacturing. The following embodiments may also be constituted by oneor a combination thereof.

The contents of the present disclosure described below may have avariety of configurations and propose only a required configurationherein, but are not limited thereto.

Electronic Device

FIG. 1 is a block diagram schematically illustrating an example of anelectronic device system. Referring to FIG. 1, an electronic device 1000may accommodate a mother board 1010 therein. Chip related components1020, network related components 1030, other components 1040, and thelike, may be physically and/or electrically connected to the motherboard 1010. These components may be connected to other components to bedescribed below to form various signal lines 1090.

The chip related components 1020 may include a memory chip such as avolatile memory (for example, a dynamic random access memory (DRAM)), anon-volatile memory (for example, a read only memory (ROM)), a flashmemory, etc.; an application processor chip such as a central processor(for example, a central processing unit (CPU)), a graphics processor(for example, a graphics processing unit (GPU)), a digital signalprocessor, a cryptographic processor, a micro processor, a microcontroller, etc.; a logic chip such as an analog-to-digital converter,an application-specific integrated circuit (ASIC), etc.; and the like.However, the chip related components 1020 are not limited thereto, andmay also include other types of chip related components. In addition,these components 1020 may be combined with each other.

The network related components 1030 may include protocols such aswireless fidelity (Wi-Fi) (Institute of Electrical and ElectronicsEngineers (IEEE) 802.11 family, or the like), worldwide interoperabilityfor microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE802.20, long term evolution (LTE), evolution data only (Ev-DO), highspeed packet access+(HSPA+), high speed downlink packet access+(HSDPA+),high speed uplink packet access+(HSUPA+), enhanced data GSM environment(EDGE), global system for mobile communications (GSM), globalpositioning system (GPS), general packet radio service (GPRS), codedivision multiple access (CDMA), time division multiple access (TDMA),digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G,5G protocols and any other wireless and wired protocols designated afterthe above-mentioned protocols. However, the network related components1030 are not limited thereto, and may also include any of a plurality ofother wireless or wired standards or protocols. In addition, thesecomponents 1030 may be combined with each other together with the chiprelated components 1020 described above.

Other components 1040 may include a high frequency inductor, a ferriteinductor, a power inductor, ferrite beads, a low temperature co-firingceramic (LTCC), an electromagnetic interference (EMI) filter, amultilayer ceramic capacitor (MLCC), and the like. However, othercomponents 1040 are not limited thereto, and may also include passivecomponents used for various other purposes, and the like. In addition,these components 1040 may be combined with each other together with thechip related components 1020 and/or the network related components 1030described above.

The electronic device 1000 may include other components that may or maynot be physically and/or electrically connected to the mother board 1010depending on a kind thereof. These other components may include, forexample, a camera 1050, an antenna 1060, a display 1070, a battery 1080,an audio codec (not illustrated), a video codec (not illustrated), apower amplifier (not illustrated), a compass (not illustrated), anaccelerometer (not illustrated), a gyroscope (not illustrated), aspeaker (not illustrated), a mass storage (for example, a hard diskdrive) (not illustrated), a compact disk (CD) (not illustrated), adigital versatile disk (DVD) (not illustrated), and the like. However,these other components are not limited thereto, and may also includeother components used for various purposes depending on a kind ofelectronic device 1000.

The electronic device 1000 may be a smartphone, a personal digitalassistant, a digital video camera, a digital still camera, a networksystem, a computer, a monitor, a tablet, a laptop, a netbook, atelevision, a video game console, a smart watch, or the like. However,the electronic device 1000 is not limited thereto, and may also be anyother electronic device processing data.

FIG. 2 is a view schematically illustrating an example of an electroniccomponent package used in an electronic device. The electronic componentpackage may be used for various purposes in the various electronicdevices 1000 as described above. For example, a main board 1110 may beaccommodated in a body 1101 of a smartphone 1100, and various electroniccomponents 1120 may be physically and/or electrically connected to themain board 1110. In addition, another component that may be or may notbe physically and/or electrically connected to the main board 1110, suchas a camera 1130, may be accommodated in the body 1101. Here, some ofthe electronic components 1120 may be the chip related components asdescribed above, and the electronic component package 100 may be, forexample, an application processor among the chip related components, butare not limited thereto.

Electronic Component Package and Method of Manufacturing the Same

FIG. 3 is a cross-sectional view schematically illustrating an exampleof an electronic component package. An electronic component package 100according to the present exemplary embodiment may include an electroniccomponent 120 disposed on a board of the electronic component packageand an encapsulant 130 electrically connected to the electroniccomponent 120 and protecting the electronic component 120. In this case,the board of the electronic component package may include a wiring part110 as a main component thereof.

The wiring part 110 may include insulating layers 111, conductivepatterns 112, and conductive vias 113, and may include signaltransferring wirings electrically connected to the electronic component120 and electrical testing wirings S electrically disconnected from theelectronic component 120. In this case, both of the signal transferringwirings and the electrical testing wirings S may include the conductivepatterns 112 and the conductive vias 113 of the wiring part 110. Theconductive patterns 112 and the conductive vias 113 of the wiring part110 included in the electrical testing wirings S among conductivepatterns 112 and the conductive vias 113 of the wiring part 110 aredenoted by conductive patterns 112S and conductive vias 113S.

The electrical testing wirings S may include the conductive patterns112S formed on both surfaces of the wiring part 110 and the conductivevias 113S electrically connecting the conductive patterns 112S to eachother, and may be provided in order to perform an electrical test of thewiring part 110 as described below. Although a case in which the wiringpart 110 has a multilayer structure has been described in the electroniccomponent package 100 according to an example, the wiring part 110 mayalso be formed of a single layer, if necessary. In addition, the wiringpart 110 may also have more layers than the single layer, depending ondesign particulars.

An insulating material that may be contained in the insulating layer 111may be a thermosetting resin such as an epoxy resin, a thermoplasticresin such as a polyimide resin, a resin having a reinforcement materialsuch as a glass fiber or an inorganic filler impregnated in thethermosetting resin and the thermoplastic resin, such as pre-preg,Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), or thelike. In addition, in a case in which a photo-imagable dielectric (PID)is used as the insulating material, the insulating layer 111 may beformed at a more reduced thickness, and a fine pattern may be moreeasily implemented. The insulating layers 111 forming respective layersin the wiring part 110 may be formed of the same material or may beformed of different materials, if necessary. Thicknesses of theinsulating layers 111 are also not particularly limited. For example,thicknesses of the insulating layers 111 except for the conductivepatterns 112 may be about 5 μm to 20 μm, and thicknesses of theinsulating layers 111 when considering thicknesses of the conductivepatterns 112 may be about 15 μm to 70 μm.

The conductive patterns 112 and 112S may also serve as a wiring patternand/or a pad pattern, and an electrically conductive material such ascopper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel(Ni), lead (Pd), or alloys thereof, may be used as materials of theconductive patterns 112 and 112S. The conductive patterns 112 mayperform various functions depending on a design of the correspondinglayer. For example, the conductive patterns 112 may serve as a ground(GND) pattern, a power (PWR) pattern, a signal (S) pattern, and thelike, as redistribution patterns. Here, the signal (S) pattern mayinclude various signals except for the ground (GND) pattern, the power(PWR) pattern, and the like, for example, data signals, and the like. Inaddition, the conductive patterns 112 may serve as a via pad, anexternal connection terminal pad, and the like, as pad patterns.Thicknesses of the conductive patterns 112 are also not particularlylimited, and may be, for example, about 10 μm to 50 μm.

Meanwhile, a surface treatment layer may be further formed on conductivepatterns 112 and 112S exposed to externally from the insulating layers111, for example, conductive patterns 112 and 112S to which theelectronic component 120 is connected, if necessary. The surfacetreatment layer is not particularly limited as long as it is known inthe related art, and may be formed by, for example, electrolytic goldplating, electroless gold plating, organic solderability preservative(OSP) or electroless tin plating, electroless silver plating,electroless nickel plating/substituted gold plating, direct immersiongold (DIG) plating, hot air solder leveling (HASL), or the like.

The conductive vias 113 and 113S may electrically connect the conductivepatterns 112 and 112S, electrode pads 121, and the like, formed ondifferent layers to each other, thereby forming an electrical pathwithin the electronic component package 100. A conductive material suchas copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel(Ni), lead (Pd), or alloys thereof, may be used as materials of theconductive vias 113 and 113S. The conductive vias 113 and 113S may alsobe completely filled with a conductive material. Alternatively, aconductive material may be formed along walls of the conductive vias 113and 113S. In addition, the conductive vias 113 and 113S may have all ofthe shapes known in the related art, such as a tapered shape in which adiameter of the via becomes smaller toward a lower surface, a reversetapered shape in which a diameter of the via becomes larger toward alower surface, a cylindrical shape, and the like.

As described above, the electrical testing wirings S may include theconductive patterns 112S and the conductive vias 113S of the wiring part110, and may be included in the board in a state in which they areelectrically disconnected from the electronic component 120, that is, ina state in which they are not electrically connected to the electroniccomponent 120. In addition, the conductive patterns 112S belonging tothe electrical testing wirings S may be electrically disconnected fromthe conductive patterns 112 belonging to the signal transferringwirings. The conductive patterns 112S included in the electrical testingwirings S may be formed on both surfaces of the wiring part 110, thatis, upper and lower surfaces of the wiring part 110 in FIG. 3. Thepurpose of this form may be to perform the electrical test through theupper portion of the wiring part 110 in a state in which a support iscoupled to a lower portion of the wiring part 110. This will bedescribed in more detail in a description of a method of manufacturingan electronic component package to be described above.

Some conductive patterns 112S of the conductive patterns of theelectrical testing wirings S to perform the electrical test of thewiring part 110 may be formed on a lower surface of the wiring part 110,and may have a form in which they do not belong to the conductivepatterns 112 belonging to the signal transferring wirings, that is, aform in which they are disconnected from the conductive patterns 112belonging to the signal transferring wirings, as illustrated in FIG. 3.This electrical disconnection structure is illustrated in more detail inFIG. 4. FIG. 4 is a plan view schematically illustrating a shape of anelectrical testing wiring in FIG. 3. The electrical testing wiring S mayinclude a conductive pattern 112S having a shape of a daisy chain inorder to perform the electrical test. Since the daisy chain is adoptedin order to perform the electrical test rather than to use a package,the daisy chain needs to be removed after the electrical test. Asillustrated in FIG. 4, a connection part C connecting the electricaltesting wiring S and another conductive pattern 112 adjacent to theelectrical testing wiring S to each other may be one of conductivepatterns formed on the lowermost surface of the wiring part 110, and maycorrespond to a testing connection pattern connecting at least twoconductive vias 113 to each other. The connection part C may bedisconnected after an electrical test, thereby forming a disconnectedregion R. As a result, the electrical testing wiring S that is notconnected to the electronic component 120 may be obtained.

As in the present exemplary embodiment, the wiring part 110 mayseparately include the electrical testing wirings S, and thus theelectrical test may be performed through an upper portion of the wiringpart 110 before the electronic component 120 is mounted, and unnecessaryconsumption of the electronic component 120 that is relatively expensivemay be reduced. That is, in a scheme according to the related art inwhich the electrical test is performed after the electronic component120 is disposed, even if a defect is generated in the wiring part ratherthan the electronic component, there was a problem that the electroniccomponent may not be used. The present inventors have intended to solvethis problem. Further, even in a case in which the electrical test isperformed before the electronic component is disposed, it was difficultto apply electrical signals to upper and lower portions of the wiringpart 110 due to the support required in a process of manufacturing thewiring part 110. Therefore, the present inventors have allowed theelectrical test to be performed through the upper portion of the wiringpart 110 even in a state in which the support is disposed by using theelectrical testing wirings S described above.

The electronic component 120 may be various active components (forexample, a diode, a vacuum tube, a transistor, and the like) or passivecomponents (for example, an inductor, a condenser, a resistor, and thelike). Alternatively, the electronic component 120 may be an integratedcircuit (IC) chip indicating a chip in which hundreds of to millions ofor more elements are integrated. The electronic component 120 may be anelectronic component in which an integrated circuit is packaged in aflip-chip form, if necessary. The integrated circuit chip may be anapplication processor chip such as a central processor (such as a CPU),a graphic processor (such as a GPU), a digital signal processor, acryptographic processor, a micro processor, a micro controller, or thelike, but is not limited thereto. In this case, although one electroniccomponent 120 is illustrated in FIG. 3, two or more electroniccomponents may also be used.

The electronic component 120 may include the electrode pads 121electrically connected to the wiring part 110. The purpose of theelectrode pad 121 may be to electrically connect the electroniccomponent 120 externally, and a material of the electrode pad 121 is notparticularly limited as long as it is a conductive material. Theconductive material may be copper (Cu), aluminum (Al), silver (Ag), tin(Sn), gold (Au), nickel (Ni), lead (Pd), or alloys thereof, but is notlimited thereto. The electrode pads 121 may be redistributed by thewiring part 110, and the wiring part 110 may be divided into first andsecond wiring parts for the purpose of redistribution as in an exemplaryembodiment to be described below. The electrode pad 121 may have anembedded form or a protruding form. In addition, the conductive pattern112 positioned at the uppermost portion of the wiring part 110 connectedto the electronic component 120 may have a form in which it is formed onan upper surface of the insulating layer 111, as illustrated in FIG. 3,or a form in which it is embedded in the insulating layer 111, that is,a form in which it does not protrude from the insulating layer 111.

In a case in which the electronic component 120 is the integratedcircuit chip, the electronic component 120 may have a body (not denotedby a reference number), a passivation layer (not denoted by a referencenumber), and the electrode pads 121. The body may be formed on the basisof, for example, an active wafer. In this case, silicon (Si), germanium(Ge), gallium arsenide (GaAs), or the like, may be used as a basicmaterial of the body. The passivation layer may serve to protect thebody from external factors, and may be formed of, for example, an oxidelayer, a nitride layer, or the like, or be formed of a double layer ofan oxide layer and a nitride layer. A conductive material such as copper(Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead(Pd), or alloys thereof, may be used as a material of the electrode pad121. A layer on which the electrode pads 121 are formed may become anactive layer.

A thickness of the electronic component 120 in a cross section thereofis not particularly limited, and may be changed depending on a kind ofelectronic component 120. For example, in a case in which the electroniccomponent is the integrated circuit chip, a thickness of the electroniccomponent may be about 100 μm to 480 μm, but is not limited thereto.

Meanwhile, as illustrated in FIG. 3, at least one conductive post 131may be disposed on the wiring part 110. In the present exemplaryembodiment, a structure in which a plurality of conductive posts 131 areprovided has been used. The conductive post 131 may serve to transfer anelectrical signal applied to an upper portion of the electroniccomponent package 100 to the wiring part 110, and is not necessarilyrequired in the present exemplary embodiment. As illustrated in FIG. 3,the plurality of conductive posts 131 may be disposed at an outer sideof the wiring part 110 so as to enclose the electronic component 120.The conductive posts 131 may serve as an electrical connection path whenanother electronic component is disposed above the electronic component120 or an external electrical signal is applied through the upperportion, and may contain a material having high electrical conductivity,such as copper, silver, or the like. In this case, as illustrated inFIG. 3, conductive vias 132 or conductive patterns 133 may be formedabove the conductive posts 131 in order to connect the electroniccomponent 120 to another electronic component, or the like, disposedabove the electronic component 120.

The encapsulant 130 may protect the electronic component 120 and theconductive post 131. For example, the encapsulant 130 may encapsulatethe electronic component 120 and the conductive post 131. A form inwhich the encapsulant 130 encapsulates the electronic component 120 andthe conductive post 131 is not particularly limited, and may be a formin which the encapsulant 130 encloses at least portions of theelectronic component 120 and the conductive post 131. Here, the meaningthat the encapsulant 130 encloses a target component is that theencapsulant 130 does not directly contact the target component due to aseparate component interposed between the encapsulant 130 and the targetcomponent as well as that the encapsulant 130 directly covers the targetcomponent.

A material of the encapsulant 130 is not particularly limited as long asthe encapsulant may serve to protect the electronic component 120 andthe conductive post 131. For example, a thermosetting resin such as anepoxy resin, a thermoplastic resin such as a polyimide resin, a resinhaving a reinforcement material such as a glass fiber or an inorganicfiller impregnated in the thermosetting resin and the thermoplasticresin, such as pre-preg, ABF, FR-4, BT, a PID resin, or the like, may beused as a material of the encapsulant 130. In addition, as describedbelow, the encapsulant 130 may be obtained by a method of stacking aresin film in a non-hardened state on the wiring part 110 and thenhardening the resin film. The encapsulant 130 may be obtained by theknown molding method such as a method of using an epoxy molding compound(EMC), or the like, in addition to the above-mentioned method.

Meanwhile, the encapsulant 130 may contain conductive particles in orderto block electromagnetic waves, if necessary. For example, theconductive particle may be any material that may block electromagneticwaves, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold(Au), nickel (Ni), lead (Pd), solder, or the like, but is notparticularly limited thereto.

The electronic component package may further include an outer layer 114disposed beneath the wiring part 110 and capable of protecting thewiring part 110 from an external physical or chemical influence, or thelike. In this case, the outer layer 114 may have opening parts exposingat least portions of the conductive patterns 112 of the wiring part 110.A material of the outer layer 114 is not particularly limited. Forexample, a solder resist may be used as a material of the outer layer140. In addition, the same material as that of the insulating layer 111of the wiring part 110 may be used as a material of the outer layer 140,and the outer layer 114 is generally formed of a single layer, but mayalso be formed of multiple layers, if necessary.

The electronic component package 100 may include connection terminals115 disposed at the lowermost portion thereof. The purpose of theconnection terminals 115 may be to physically and/or electricallyexternally connect the electronic component package 100. For example,the electronic component package 100 may be mounted on the main board ofthe electronic device through the connection terminals 115. Theconnection terminals 115 may be connected to the conductive patterns 112through the opening parts formed in the outer layer 114. Therefore, theconnection terminals 115 may also be electrically connected to theelectronic component 120. The connection terminal 115 may be formed of aconductive material, such as copper (Cu), aluminum (Al), silver (Ag),tin (Sn), gold (Au), nickel (Ni), lead (Pd), solder, or the like, but isnot particularly limited thereto. The connection terminal 115 may be aland, a ball, a pin, or the like. The connection terminal 115 may beformed of multiple layers or a single layer. In a case in which theconnection terminal 115 is formed of multiple layers, the connectionterminal 115 may contain a copper pillar and a solder, and in a case inwhich the connection terminal 115 is formed of a single layer, theconnection terminal 115 may contain a tin-silver solder or copper.However, this is only an example, and the connection terminal 115 is notlimited thereto.

Meanwhile, some of the external connection terminals 115 may be disposedin a fan-out region. The fan-out region is defined as a region exceptfor a region in which the electronic component is disposed. That is, theelectronic component package 100 according to an example may be afan-out package. The fan-out package may have reliability greater thanthat of a fan-in package, may implement a plurality of I/O terminals,and may easily perform 3D interconnection. In addition, since thefan-out package may be mounted on the electronic device without using aseparate substrate as compared to a ball grid array (BGA) package, aland grid array (LGA) package, or the like, the fan-out package may bemanufactured at a reduced thickness, and may have excellent pricecompetitiveness.

The number, an interval, a disposition form, and the like, of connectionterminals 115 are not particularly limited, and may be sufficientlymodified depending on design particulars by those skilled in the art.For example, the number of connection terminals 115 may be several tento several thousand depending on the number of electrode pads 121 of theelectronic component 120. However, the number of connection terminals115 is not limited thereto, and may also be several ten to severalthousand or more or several ten to several thousand or less.

Hereinafter, a board of an electronic component package and a method ofmanufacturing an electronic component package according to an exemplaryembodiment in the present disclosure will be described. The structure ofthe electronic component package according to the above-mentionedexemplary embodiment or a modified example may be more clearlyunderstood through a description of a method of manufacturing anelectronic component package.

FIGS. 5 through 12 are views schematically illustrating a board for anelectronic component package and a method of manufacturing an electroniccomponent package using the same according to an exemplary embodiment inthe present disclosure.

First, as illustrated in FIG. 5, the wiring part 110 may be formed on asupport 160. The purpose of the support 160 may be to handle the wiringpart 110 having a relatively reduced thickness, and a material of thesupport 160 is not particularly limited as long as it may support thewiring part 110. The support 160 may have a multilayer structure, andmay include a release layer, a metal layer, and the like, so as to beeasily removed from the wiring part 110 in a subsequent process. In thepresent exemplary embodiment, an electrical test of the wiring part 110may be performed in a state in which the support 160 is coupled to thewiring part 110. To this end, the uppermost portion of the support 160may be formed of a material having an electrical insulation property.

The insulating layer 111, the conductive patterns 112, and theconductive vias 113 of the wiring part 110 may be formed depending onintended shapes, and a process of forming the insulating layer 111, theconductive patterns 112, and the conductive vias 113 may be repeated therequired number of times. In detail, the insulating layer 111 may beformed by a known method, such as a method of laminating a precursor ofthe insulating layer 111 and then hardening the precursor, a method ofapplying a material for forming the insulating layer 111 and thenhardening the material, or the like. As the method of laminating theprecursor, a method of performing a hot press process of pressing theprecursor for a predetermined time at a high temperature, decompressingthe precursor, and then cooling the precursor to a room temperature,cooling the precursor in a cold press process, and then separating awork tool, or the like, may be used. As the method of applying thematerial, for example, a screen printing method of applying ink bysqueeze, a spray printing method of applying ink in a mist form, or thelike, may be used. The hardening process, which is a post-process, maybe a process of drying the material so as not to be completely hardenedin order to use a photolithography method, or the like.

The conductive patterns 112 and the conductive vias 113 may also beformed by the known method. First, via holes (not illustrated) may beformed using the mechanical drill and/or the laser drill describedabove. Alternatively, the via holes may also be formed by aphotolithography method in a case in which the insulating layer 111contains the PID, or the like. The conductive patterns 112 and theconductive vias 113 may also be formed by electrolytic copper plating,electroless copper plating, or the like, using a dry film pattern.

As described above, in the present exemplary embodiment, the conductivepatterns 112S and the conductive vias 113S may form the electricaltesting wirings S. However, the electrical testing wirings S may be in astate in which they are connected to other conductive patterns 112 andconductive vias 113 in order to perform an electrical test for thewiring part 110 unlike a final structure. These connection parts Cconnected to the electrical testing wirings S may be formed beneath thewiring part 110, as illustrated in FIG. 5. In a case in which theconnection parts C are formed beneath the wiring part 110, ashort-circuit process for electrically disconnecting the electricaltesting wirings S from the electronic component 120 may be easilyexecuted in a subsequent process.

Next, as illustrated in FIG. 6, it may be confirmed whether or not adefect is present in the wiring part 110 in terms of electricalconnection. To this end, a testing jig 161 may be connected to theconductive patterns 112 on the wiring part 110. In this case, thetesting jig 161 may include a plurality of tips 162. The plurality oftips 162 may be disposed at positions corresponding to at least some ofthe conductive patterns 112 on the wiring part 110.

As described above, the electrical testing wirings S provided in orderto perform the electrical test may be in a state in which they areelectrically connected to the conductive patterns 112 and the conductivevias 113 to be connected to the electronic component, and the conductivepatterns 112S of the electrical testing wirings S may be formed on thewiring part 110. Due to this structure, even in a case in which anelectrical signal is not applied to the upper and lower portions of thewiring part 110, that is, even in a state in which the support 160 iscoupled to the wiring part 110, the electrical test may be performedthrough only the conductive patterns 112 disposed on an upper surface ofthe wiring part 110, and the present test process may be executed beforethe electronic component is mounted. The wiring part 110 determined tobe unsatisfactory in the present test process may be discarded or reusedfor another purpose, and a subsequent process is not performed on thewiring part 110 determined to be unsatisfactory, and thus a process costmay be reduced.

Next, as illustrated in FIG. 7, the conductive posts 131 having a pillarshape may be formed on the wiring part 110. The conductive posts 131 maybe electrically connected to the conductive patterns 112 and theconductive vias 113 of the wiring part 110. As described above, theconductive post 131 may be formed of a material such as copper, silver,or the like, and may be formed of an appropriate plating method. As amethod of forming the conductive post 131, another method may be used inaddition to the plating method. For example, a method of bonding astructure having a pillar shape to the wiring part 110 may beconsidered.

Meanwhile, the electrical testing process described above may also beexecuted after the conductive posts 131 are formed. That is, before theelectronic component 120 is mounted on the wiring part 110, theelectrical test for the wiring part 110 and the conductive posts 131 maybe performed to check whether or not a defect is generated in the wiringpart 110 and the conductive posts 131 at a time.

Next, as illustrated in FIG. 8, the electronic component 120 may bedisposed on the wiring part 110, and may be electrically connected tothe wiring part 110. In this case, a position at which the electroniccomponent 120 is disposed is not particularly limited. However, it maybe preferable that the electronic component 120 is mounted on the wiringpart 110 in a state in which it is not connected to the electricaltesting wirings S. In addition, in a case in which the electricaltesting wirings S are positioned directly beneath the electroniccomponent 120, the electrical testing wirings S may be unintentionallyconnected to the electronic component 120. Therefore, it may bepreferable that a position at which the electronic component 120 ismounted is adjusted so that the electrical testing wirings S arepositioned in the vicinity of the electronic component 120. Meanwhile,as described above, the electronic component 120 may be disposed to beenclosed by the plurality of conductive posts 131. In order to provide astable mounting structure, a conductive adhesion material may be usedbetween the electrode pads 121 of the electronic component 120 and theconductive patterns 112 of the wiring part 110.

Next, as illustrated in FIG. 9, the encapsulant encapsulating theelectronic component 120 and the conductive posts 131 may be formed. Asan example of a method of forming the encapsulant 130, a method ofstacking a resin film in a non-hardened state on the wiring part 110 andthen hardening the resin film may be used. In this case, a metal thinfilm may be formed on a surface of the resin film, that is, an uppersurface of the resin film in FIG. 8. The metal thin film may be used tolater form a wiring pattern. As a specific example of the resin film, aresin coated copper (RCC) may be used. After the encapsulant 130 isformed, the conductive vias 132 and the conductive patterns 133 may beformed to be connected to the conductive posts 131. Detailed contents ofa process of forming the conductive vias 132 and the conductive patterns133 will be described below.

Next, as illustrated in FIG. 10, the support 160 may be separated fromthe wiring part 110. In this case, an etching process, a desmearprocess, or the like, used in the related art may be appropriatelyutilized. In addition, as described above, testing connection patterns,that is, the connection parts C, may be disconnected in order toelectrically isolate the electrical testing wirings S. Thisdisconnection process will be described in detail with reference to FIG.11.

As illustrated in FIG. 11, after the conductive patterns 112 are exposedby the etching process, the desmear process, or the like, describedabove, a mask layer 170 such as a dry film photo-resist (DFR) film maybe formed. The mask layer 170 may have a form in which regions to bedisconnected are opened. The conductive patterns 112 may be etchedthrough this open region to disconnect the connection parts, therebyforming disconnected regions that may electrically isolate theelectrical testing wirings S. Therefore, an originally intended wiringform may be obtained.

Then, the outer layer 114 covering the conductive patterns 112 may beformed. The outer layer 114 may cover the conductive patterns 112Sincluded in the electrical testing wirings S so as not to be externallyexposed, and may have the opening parts exposing at least portions ofthe conductive patterns 112 connected to the electronic component 120.

The outer layer 114 may be formed by a method of laminating a precursorof the outer layer 114 and then hardening the precursor, a method ofapplying a raw material for forming the outer layer 114 and thenhardening the raw material, or the like. Then, the opening parts may beformed in the outer layer 114, and the connection terminals 115described with reference to FIG. 3 may be formed to fill in the openingparts. A method of forming the connection terminals 115 is notparticularly limited. That is, the connection terminals 115 may beformed by a method well known in the related art depending on astructure or a form of the connection terminals 115. The connectionterminals 115 may be fixed by reflow, portions of the connectionterminals 115 may be embedded in the outer layer 114 in order to enhancefixing force, and the remaining portions of the connection terminals 115may be externally exposed, whereby reliability may be improved.

Meanwhile, as a modified example, as illustrated in FIG. 12, anadditional electronic component 140 may be disposed on the encapsulant130, and an additional encapsulant 150 covering the additionalelectronic component 140 may be formed, whereby a package-on-package(POP) structure may be obtained. Hereinafter, in order to distinguishthe electronic component 120 and the additional electronic component 140from each other and distinguish the encapsulant 130 and the additionalencapsulant 150 from each other, the electronic component 120 will bereferred to as a first electronic component, the additional electroniccomponent 140 will be referred to as a second electronic component, theencapsulant 130 will be referred to as a first encapsulant, and theadditional encapsulant 150 will be referred to as a second encapsulant,if necessary.

The second electronic component 140 may be various active components orpassive components, similar to the first electronic component 120, andmay be, for example, a memory element, or the like. As described above,the second electronic component 140 may be electrically connected to theconductive posts 131. Although connection between the second electroniccomponent and the conductive posts 131 through wires 151 has beenillustrated in FIG. 12, the connection between the second electroniccomponent and the conductive posts 131 through the wires 151 is only anexample. That is, the second electronic component and the conductiveposts 131 may be connected to each other by another connection method,for example, a flip-chip bonding method, or the like. In addition,although one electronic component 120 has been illustrated in FIG. 3,two or more electronic components may also be used.

The second encapsulant 150 may encapsulate the second electroniccomponent 140 in order to protect the second electronic component 140,similar to the first encapsulant 130. In this case, as seen from a formillustrated in FIG. 12, the first encapsulant 130 and the secondencapsulant 150 may contact each other. In detail, an upper surface ofthe first encapsulant 130 and a lower surface of the second encapsulant150 may contact each other in at least a partial region, and by thisstructure a compact package structure may be obtained even in a case inwhich a plurality of electronic components are used. A material of thesecond encapsulant 150 is not particularly limited as long as the secondencapsulant 150 may perform this function. For example, the secondencapsulant 150 may be formed by EMC molding using an insulating resin.In addition, the second encapsulant 150 may also be formed of the samematerial as that of the first encapsulant 130. Further, the secondencapsulant 150 may be obtained by the same method as the method offorming the first encapsulant 130, for example, the method of stackingthe resin film in the non-hardened state.

Meanwhile, the present process of mounting the additional electroniccomponent 140 may be executed in a state in which the support 160 iscoupled to the wiring part 110, as illustrated in FIG. 12, or may beexecuted in a state in which the support 160 is separated from thewiring part 110. In addition, before the second electronic component 140is mounted, the electrical test may be performed once more through theconductive patterns 133 on the encapsulant 130, and in the state inwhich the support 160 is separated from the wiring part 110, theelectrical test may be performed using both of the conductive patterns133 on the encapsulant 130 and the conductive pattern 112 beneath thewiring part 110. In a subsequent process, the above-mentioned processesmay be used, thereby appropriately completing a POP structure.

Hereinafter, another example of a method of manufacturing an electroniccomponent package suggested in the present disclosure will be described.FIGS. 13 through 18 are views schematically illustrating a method ofmanufacturing an electronic component package according to anotherexemplary embodiment in the present disclosure. The method ofmanufacturing an electronic component package according to the presentexemplary embodiment is mainly different from the method ofmanufacturing an electronic component package according to the exemplaryembodiment described above in that two wiring parts having differentcharacteristics are used. However, a technical spirit that is notopposite to that of the exemplary embodiment described above in contentsthat will be described in association with a method of manufacturing anelectronic component package below may also be adopted in the exemplaryembodiment described above.

First, as illustrated in FIG. 13, a first wiring part 210 a may beformed on a support 260. The first wiring part 210 a may include aninsulating layer 211 a, conductive patterns 212 a (see FIG. 14), andconductive vias 213 a (see FIG. 14). In this case, the first wiring part210 a may include electrical testing wirings S for performing anelectrical test. Since the first wiring part 210 a may be obtained bythe method described in the exemplary embodiment described above, anoverlapping description will be omitted.

Next, as illustrated in FIG. 14, a second wiring part 210 b may beformed on the first wiring part 210 a. Similar to the first wiring part210 a, the second wiring part 210 b may include an insulating layer 211b, conductive patterns 212 b, and conductive vias 213 b, and electricaltesting wirings S for performing an electrical test may be formed in astate in which they are connected to the first wiring part 210 a. Thesecond wiring part 210 b, which is disposed more closely to anelectronic component as compared to the first wiring part 210 a, may beutilized as a redistribution layer. To this end, the smallest intervalbetween the conductive patterns 212 b included in the second wiring part210 b may be smaller than the smallest interval between the conductivepatterns 212 a included in the first wiring part 210 a. To this end,materials of the insulating layers 211 a and 211 b each included in thefirst and second wiring parts 210 a and 210 b may be different from eachother. In a case of the second wiring part 210 b in which fine patternsneed to be formed, the insulating layer 211 b may be formed of aphoto-curable material so that a photolithography process may be used.The insulating layer 211 a included in the first wiring part 210 a maybe formed of the same material as that of the insulating layer 211 b ofthe second wiring part 210 b. However, the insulating layer 211 aincluded in the first wiring part 210 a may be formed of a materialdifferent from that of the insulating layer 211 b of the second wiringpart 210 b in consideration of other characteristics of the electroniccomponent package. For example, the insulating layer 211 a included inthe first wiring part 210 a may be formed of a material includingpre-preg or ABF in consideration of warpage rigidity characteristics, orthe like.

Meanwhile, unlike the exemplary embodiment described above, in thepresent exemplary embodiment, electrode pads 214 b having a protrudingform have been used. The insulating layer 211 b may be etched at anappropriate thickness in order to obtain the electrode pads 214 b havingthe protruding form. It may be appropriate in forming fine patterns touse electrode pads having an embedded form, and in a case of using theelectrode pads having the protruding form, close adhesion between theelectrode pad and the electronic component may be improved. Therefore,electrode pads having an appropriate form, if necessary, may be used.

Next, although not separately illustrated, also in the present exemplaryembodiment, the electrical test may be performed through an upperportion of the second wiring part 210 b, as described above withreference to FIG. 6. When it is determined that a defect is present inat least one of the first and second wiring parts 210 a and 210 b in thepresent test process, a subsequent process may not be performed, andthus process efficiency may be increased.

As illustrated in FIG. 15, conductive posts 231 may be formed. A processof forming the conductive posts 231 will be described in more detail.First, a mask layer 280 such as a DFR film may be formed on the wiringparts 210 a and 210 b, and regions in which the conductive posts are tobe formed may be removed. Then, the removed regions may be filled by aprocess such as a plating process, a sputtering process, a pasteapplying process, or the like, to form the conductive posts 231. Then,the mask layer 280 may be removed. Therefore, a region in which theelectronic component is mounted may be provided. In addition, similar tothe exemplary embodiment described above, the electrical test for thewiring parts 210 a and 210 b, and the like, may be performed through theconductive posts 231 after the conductive posts 231 are formed, ifnecessary.

Then, as illustrated in FIG. 16, an electronic component 220 includingelectrode pads 221 may be mounted on the wiring parts 210 a and 210 b,and may be bonded to the wiring parts by applying a conductive adhesive222 between the electrode pads 221 and 214 b.

Next, as illustrated in FIG. 17, an encapsulant 230 may be formed. Inthis case, as described above, a resin coated copper (RCC) in anon-hardened state may be used. After the encapsulant 230 is formed, aconductive structure for electrical connection to an additionalelectronic component, or the like, mounted later may be formed. To thisend, a method of partially removing the encapsulant 230 to form holes Hexposing the conductive posts 231 and then forming conductive vias 232connecting conductive patterns 233 and the conductive posts 231 to eachother may be used.

Next, as illustrated in FIG. 18, an additional or second electroniccomponent 240 may be disposed on the encapsulant 230, and an additionalor second encapsulant 250 covering the additional or second electroniccomponent 240 may be formed. However, the present process may beomitted. That is, a subsequent process may be performed in a state inwhich the additional electronic component 240 and the additionalencapsulant 250 are not formed. Then, similar to the exemplaryembodiment described above, the support 260 may be removed, andconnection parts, which are testing patterns connected to otherconductive patterns 212 a, may be removed so as to electrically isolatethe electrical testing wirings S. Then, similar to the exemplaryembodiment described above, an outer layer and connection terminals maybe formed, whereby a package structure may be obtained.

As set forth above, according to an exemplary embodiment in the presentdisclosure, the electronic component package may have a compact size,and may have high utilization even in a case in which a plurality ofelectronic components are used. In addition, the electrical test may beperformed before the electronic component is mounted, wherebymanufacturing efficiency may be significantly improved. Further, theelectronic component package described above may be efficientlymanufactured by the method of manufacturing an electronic componentpackage according to an exemplary embodiment in the present disclosure.

While exemplary embodiments have been shown and described above, it willbe apparent to those skilled in the art that modifications andvariations could be made without departing from the scope of the presentinvention as defined by the appended claims.

What is claimed is:
 1. An electronic component package comprising: awiring part; an electronic component disposed on the wiring part; and anencapsulant protecting the electronic component, wherein the wiring partincludes an insulating layer and a signal transferring wiringelectrically connected to the electronic component, an uppermost portionof the signal transferring wiring is disposed on an uppermost portion ofthe insulating layer and is partially embedded in the encapsulant, and alowermost portion of the signal transferring wiring is partiallyembedded in a lowermost portion of the insulating layer.
 2. Theelectronic component package of claim 1, further comprising a pluralityof conductive posts disposed on the uppermost portion of the signaltransferring wiring and electrically connected therewith.
 3. Theelectronic component package of claim 2, wherein the electroniccomponent is surrounded by the plurality of conductive posts.
 4. Theelectronic component package of claim 2, further comprising conductivevias disposed on the plurality of conductive posts, being electricallyconnected therewith, and partially embedded in the encapsulant.
 5. Theelectronic component package of claim 4, further comprising conductivepatterns disposed on the conductive vias and being electricallyconnected therewith.
 6. The electronic component package of claim 1,wherein the wiring part has a plurality of stacked insulating layers. 7.The electronic component package of claim 1, wherein the wiring partfurther has an electrical testing wiring electrically disconnected fromthe electronic component.
 8. The electronic component package of claim7, wherein conductive patterns belonging to the electrical testingwiring are electrically disconnected from conductive patterns belongingto the signal transferring wiring.
 9. The electronic component packageof claim 1, wherein the wiring part includes a first wiring part and asecond wiring part between the first wiring part and the electroniccomponent, and the smallest interval between conductive patternsincluded in the second wiring part is smaller than the smallest intervalbetween conductive patterns included in the first wiring part.
 10. Theelectronic component package of claim 9, wherein materials of insulatinglayers respectively included in the first and second wiring parts aredifferent from each other.
 11. The electronic component package of claim10, wherein the insulating layer included in the second wiring part isformed of a photo-curable material, and the insulating layer included inthe first wiring part is formed of a material including pre-preg orAjinomoto build-up film (ABF).